A Method to Derive SSO Design Rule Considering Jitter Constraint

Koutaro HACHIYA  Hiroyuki KOBAYASHI  Takaaki OKUMURA  Takashi SATO  Hiroki OKA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A    No.4    pp.865-872
Publication Date: 2006/04/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.4.865
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
simultaneous switching output,  simultaneous switching noise,  jitter,  ASIC,  

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A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.