A Practical Analog BIST Cooperated with an LSI Tester

Takanori KOMURO  Naoto HAYASAKA  Haruo KOBAYASHI  Hiroshi SAKAYORI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A    No.2    pp.465-468
Publication Date: 2006/02/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.2.465
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
LSI testing,  analog circuit,  BIST,  equivalent-time sampling,  sampler,  

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Summary: 
This paper proposes a new approach for analog portion testing, which can meet requirements for high-speed and high-accuracy testing simultaneously with reasonable cost. The key concept of the new method is cooperation of an LSI tester and some circuitry built in a target SoC device. We will explain the operation principle of the proposed method. The proposed method can be one of the methods to overcome today's expensive production test of analog portion on SoC (System on Chip) devices which heavily depends on LSI tester capability and will become harder in near future.