Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer SciencesVol.E89-ANo.2pp.385-390 Publication Date: 2006/02/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.2.385 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: delay-locked loop (DLL), false lock, frequency range, duty cycle, digital camera,
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Summary: A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 465 MHz (16) and a timing resolution of 9(40 stages).