A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

Junichi MIYAKOSHI  Yuichiro MURACHI  Tetsuro MATSUNO  Masaki HAMAMOTO  Takahiro IINUMA  Tomokazu ISHIHARA  Hiroshi KAWAGUCHI  Masayuki MIYAMA  Masahiko YOSHIMOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.12   pp.3623-3633
Publication Date: 2006/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.12.3623
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
low power,  motion estimation,  H.264,  SIMD,  systolic array,  

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We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352288) 30-fps to QCIF (176144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.83.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 µW in a QCIF 15-fps sequence with one reference picture.