Statistical Modeling of a Via Distribution for Yield Estimation

Takumi UEZONO  Kenichi OKADA  Kazuya MASU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.12   pp.3579-3584
Publication Date: 2006/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.12.3579
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
via distribution,  yield estimation,  wire length distribution,  

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In this paper, we propose a via distribution model for yield estimation. This model expresses a relationship between the number of vias and wire length. We also provide an estimate for the total number of vias in a circuit, derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from the gate-level netlist and the layout area. We extract model parameters from the commercial chips designed for 0.18-µm and 0.13-µm CMOS processes, and demonstrate the yield degradation caused by vias.