A Hardware Algorithm for Integer Division Using the SD2 Representation

Naofumi TAKAGI  Shunsuke KADOWAKI  Kazuyoshi TAKAGI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A   No.10   pp.2874-2881
Publication Date: 2006/10/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.10.2874
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
computer arithmetic,  division,  integer division,  hardware algorithm,  signed-digit representation,  VLSI,  

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A hardware algorithm for integer division is proposed. It is based on the radix-2 non-restoring division algorithm. Fast computation is achieved by the use of the radix-2 signed-digit (SD2) representation. The algorithm does not require normalization of the divisor, and hence, does not require an area-consuming leading-one (or zero) detection nor shifts of variable-amount. Combinational (unfolded) implementation of the algorithm yields a regularly structured array divider, and sequential implementation yields compact dividers.