A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition

Tso-Bing JUANG  Shen-Fu HSIAO  Ming-Yu TSAI  Jenq-Shiun JAN  

IEICE TRANSACTIONS on Information and Systems   Vol.E88-D    No.7    pp.1464-1471
Publication Date: 2005/07/01
Online ISSN: 
DOI: 10.1093/ietisy/e88-d.7.1464
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
multipliers,  multiplier and accumulator (MAC),  partial product compression,  final adder partition,  arithmetic functional units,  datapath generation,  

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In this paper, a cell-driven multiplier generator is developed that can produce high-performance gate-level netlists for multiplier-related arithmetic functional units, including multipliers, multiplier and accumulators (MAC) and dot product calculator. The generator optimizes the speed/area performance both in the partial product compression and in the final addition stage for the specified process technology. In addition to the conventional CMOS full adder cells, we have also designed fast compression elements based on pass-transistor logic for further performance improvement of the generated multipliers. Simulation results show that our proposed generator could produce better multiplier-related functional units compared to those generated using Synopsys Designware library or other previously proposed approaches.