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Low Latency Four-Flop Synchronizer with the Handshake Interface
Suk-Jin KIM Jeong-Gun LEE Kiseon KIM
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Communications and Wireless Systems
synchronizer, two-flop, clock domain, SoC,
Full Text: PDF(445.9KB)>>
This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.