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Delay Fault Testing of Processor Cores in Functional Mode
Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/03/01
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
processor test, delay fault testing, software-based self-test, at-speed test,
Full Text: PDF(331.2KB)>>
This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.