A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector

Rong-Jyi YANG
Shen-Iuan LIU

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.8    pp.1726-1730
Publication Date: 2005/08/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.8.1726
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
DLL,  CDR,  dual loop,  

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A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.