A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver

Yong-Hsiang HSIEH  Wei-Yi HU  Wen-Kai LI  Shin-Ming LIN  Chao-Liang CHEN  David J. CHEN  Sao-Jie CHEN  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.8   pp.1716-1722
Publication Date: 2005/08/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.8.1716
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
802.11b,  CMOS RF transceiver,  image-reject mixer,  2.4 GHz transceiver,  filter reuse,  IF circuits reuse,  

Full Text: PDF>>
Buy this Article

This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.