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Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages
Takeshi YUASA Tamotsu NISHINO Hideyuki OH-HASHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2005/07/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Recent Technologies of Microwave and Millimeter-Wave Devices Focusing on Miniaturization and Advancement in Performance with Their Applications)
Category: Passive Circuits
multi-layered package, via-hole, coupling, mode-matching technique,
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In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.