A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs

Rong-Jyi YANG  Shen-Iuan LIU  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.6   pp.1248-1252
Publication Date: 2005/06/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.6.1248
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
DLL,  clock generation,  wide range,  duty cycle correction,  

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A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.