A Low Jitter ADPLL for Mobile Applications

Kwang-Jin LEE  Hyo-Chang KIM  Uk-Rae CHO  Hyun-Geun BYUN  Suki KIM  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.6   pp.1241-1247
Publication Date: 2005/06/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.6.1241
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
ADPLL,  All Digital PLL,  DCO,  

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This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 µm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.