A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula

Hideki SHIMA
Toshimasa MATSUOKA

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.5    pp.824-828
Publication Date: 2005/05/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.5.824
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures)
spiral inductors,  interconnect,  closed-form expression,  inductance extraction,  analytical technique,  

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A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.