Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs

Takeo MATSUKI  Kazuyoshi TORII  Takeshi MAEDA  Yasushi AKASAKA  Kiyoshi HAYASHI  Naoki KASAI  Tsunetoshi ARIKADO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.5   pp.804-810
Publication Date: 2005/05/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.5.804
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
MOSFET,  high-k,  metal-gate,  gate-last,  

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Summary: 
We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.