A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential

Dondee NAVARRO  Takeshi MIZOGUCHI  Masami SUETAKE  Kazuya HISAMITSU  Hiroaki UENO  Mitiko MIURA-MATTAUSCH  Hans Jurgen MATTAUSCH  Shigetaka KUMASHIRO  Tetsuya YAMAGUCHI  Kyoji YAMASHITA  Noriaki NAKAYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.5   pp.1079-1086
Publication Date: 2005/05/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.5.1079
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
pinch-off region,  channel-length modulation,  overlap capacitance,  surface-potential-based modeling,  circuit simulation,  

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Summary: 
We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100 nm pocket-implant technologies as a function of bias condition and gate length.