Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems

Kwang-Hyun BAEK

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.5    pp.1053-1060
Publication Date: 2005/05/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.5.1053
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
high-speed D/A converter,  design methodology,  interconnect modeling,  behavioral modeling,  mixed-mode VLSI,  

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This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.