Charging and Discharging Characteristics of Stacked Floating Gates of Silicon Quantum Dots

Mitsuhisa IKEDA

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.4    pp.709-712
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.709
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices)
Category: Nanomaterials and Quantum-Effect Devices
silicon quantum dot,  MOS memory,  floating gate,  Coulomb blockade,  

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We have fabricated Al-gate MOS capacitors with a Si quantum-dots (Si-QDs) floating gate, the number of dots was changed in the range of 1.6-4.81011 cm-2 in areal density with repeating the formation of Si dots and their surface oxidation a couple of times. The capacitance-voltage (C-V) characteristics of Si-QDs floating gate MOS capacitors on p-Si(100) confirm that, with increasing number of dots density, the flat-band voltage shift due to electron charging in Si-QDs is increased and the accumulation capacitance is decreased. Also, in the negative bias region beyond the flat-band condition, the voltage shift in the C-V curves due to the emission of valence electrons from intrinsic Si-QDs was observed with no hysterisis presumably because holes generated in Si-QDs can smoothly recombine with electrons tunneling through the 2.8 nm-thick bottom SiO2. In addition, we have demonstrated the charge retention characteristic improves in the Si-QDs stacked structure.