For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
High Ruggedness Power MOSFET Design by a Self-Align p+ Process
Feng-Tso CHIEN Ming-Hung LAI Shih-Tzung SU Kou-Way TU Ching-Ling CHENG
IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices)
Category: Power Devices
Power MOSFET, unclamped inductive load switching (UIS), ruggedness,
Full Text: PDF(660.5KB)>>
A new high ruggedness Power MOSFET structure with a planar oxide self align p+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p+ MASK process and contact p+ implant process. It is shown that the self align implant structure with a wide p+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p+ implant process is improved about 355% as compared to the traditional one.