Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh

Hideyuki NODA  Kazunari INOUE  Hans Jurgen MATTAUSCH  Tetsushi KOIDE  Katsumi DOSAKA  Kazutami ARIMOTO  Kazuyasu FUJISHIMA  Kenji ANAMI  Tsutomu YOSHIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.4   pp.622-629
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.622
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
CMOS,  Ternary CAM,  network,  refresh,  

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This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.