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The Umbrella Cell: A High-Density 2T Cell for SOC Applications
Satoru AKIYAMA Takao WATANABE Nobuhiro OODAIRA Tsuyoshi ISHIKAWA Digh HISAMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
SOC, on-chip memory, low-voltage, planar capacitor, logic-process,
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To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.