Power Optimization of an 8051-Compliant IP Microcontroller

Luca FANUCCI  Sergio SAPONARA  Alexander MORELLO  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.4   pp.597-600
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.597
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
low-power,  VLSI,  intellectual property (IP) cells,  8051 microcontroller,  

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Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.