Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits

Kenji SHIMAZAKI  Makoto NAGATA  Takeshi OKUMOTO  Shozo HIRANO  Hiroyuki TSUJIKAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.4   pp.589-596
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.589
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
substrate noise,  power-supply noise,  ground noise,  noise detector,  dynamic IR drop,  

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Summary: 
Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.