A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

Junichi MIYAKOSHI  Yuichiro MURACHI  Koji HAMANO  Tetsuro MATSUNO  Masayuki MIYAMA  Masahiko YOSHIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.4    pp.559-569
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.559
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
motion estimation,  MPEG,  H.264,  block-matching,  

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This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.