Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

Farzan FALLAH  Massoud PEDRAM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.4   pp.509-519
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.509
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
power,  leakage,  standby,  sleep mode,  subthreshold,  

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Summary: 
In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.