CMOS Radio Design for Complete Single Chip GPS SoC

Norihito SUZUKI  Takahide KADOYAMA  Masayuki KATAKURA  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.4   pp.496-501
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.496
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Analog
GPS,  radio,  CMOS,  SoC,  substrate coupling noise,  low power,  

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A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.