A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL

Takahito MIYAZAKI  Masanori HASHIMOTO  Hidetoshi ONODERA  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.3   pp.437-444
Publication Date: 2005/03/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.3.437
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
clock generation PLL,  LC oscillator,  ring oscillator,  performance prediction,  jitter,  power consumption,  chip area,  

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This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics. In the future, it is predicted that operating frequency will rapidly increase and supply voltage will dramatically decrease. Besides, rigid noise performances will be required. In this condition, it is not clear neither how performances of both PLLs will change nor the performance differences between both PLLs will change. This paper predicts and compares future performances of PLLs using a RingVCO and an LCVCO with a qualitative evaluation by an analytical approach and with design experiments based on predicted process parameters. Our discussion reveals that the relative performance difference between both PLLs will be unchanged. As technology advances, power dissipation and chip area of both PLLs favorably decrease, while, noise characteristics of both PLLs degrade, which indicates low noise PLL circuit design will be more important.