A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band

Seok KANG  Beomsup KIM  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.1   pp.149-153
Publication Date: 2005/01/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.1.149
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
frequency synthesis,  delay-locked loop,  edge combine,  

Full Text: PDF>>
Buy this Article

This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) comparison frequency. This architecture has been verified by implementing the synthesizer in a 0.18 µm CMOS technology.