A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros

Akira YAMAZAKI  Fukashi MORISHITA  Naoya WATANABE  Teruhiko AMANO  Masaru HARAGUCHI  Hideyuki NODA  Atsushi HACHISUKA  Katsumi DOSAKA  Kazutami ARIMOTO  Setsuo WAKE  Hideyuki OZAKI  Tsutomu YOSHIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.10    pp.2020-2027
Publication Date: 2005/10/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.10.2020
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
embedded memory,  DRAM,  voltage margin,  low voltage,  system on chip,  

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The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.