DMFQ: Hardware Design of Flow-Based Queue Management Scheme for Improving the Fairness

Norio YAMAGAKI  Hideki TODE  Koso MURAKAMI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E88-B   No.4   pp.1413-1423
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietcom/e88-b.4.1413
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Internet Technology V)
Category: 
Keyword: 
Internet router,  active queue management,  fairness,  hardware design,  

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Summary: 
Recently, various types of traffic have increased on the Internet with the development of broadband networks. However, it is difficult to guarantee QoS for each traffic type in current network environments. Moreover, it has been reported that bandwidth can be allocated to flows unfairly, and this can be an important issue for QoS guarantees. Therefore, we have proposed a flow-based queue management scheme, called Dual Metrics Fair Queueing (DMFQ), to improve the fairness and QoS per flow. DMFQ discards arrival packets by considering not only the arrival rate per flow but also the flow succession time. In addition, we have confirmed the effectiveness of DMFQ through several computer simulations. In this paper, we implement DMFQ with hardware for high-speed operation. Concretely, we propose the design policies and show the hardware design results.