Timing-Driven Placement Based on Path Topology Analysis

Feng CHENG  Junfa MAO  Xiaochun LI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.8   pp.2227-2230
Publication Date: 2005/08/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.8.2227
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
timing-driven placement,  interconnect,  delay,  critical path,  

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A timing-driven placement algorithm based on path topology analysis is presented. The optimization for path delay is transformed into cell location optimization. The algorithm pays much attention on path topologies and applies an effective force directed method to find cell target locations. Total wire length optimization is combined with the timing-driven placement algorithm. MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks are experimented and results show that our timing-driven placement algorithm can make the longest path delay improve up to 13% compared with wirelength driven placement.