High-Speed Low Input Impedance CMOS Current Comparator

Varakorn KASEMSUWAN  Surachet KHUCHAROENSIN  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.6   pp.1549-1553
Publication Date: 2005/06/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.6.1549
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
Keyword: 
current-mode,  current comparator,  low input impedance,  

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Summary: 
A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.