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High-Speed Low Input Impedance CMOS Current Comparator
Varakorn KASEMSUWAN Surachet KHUCHAROENSIN
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
current-mode, current comparator, low input impedance,
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A simple high-speed low input impedance CMOS current comparator is presented. The circuit uses improved Wilson current-mirror to perform subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with standard 0.5 µm CMOS technology. Simulation results demonstrate propagation delay of 1.02 ns, average power consumption of 0.9 mW, and input impedance of 137 Ω for 0.1 µA input current at the supply voltage of 3 V.