Clock-Free MTCMOS Flip-Flops with High Speed and Low Power

Bong Hyun LEE  Young Hwan KIM  Kwang-Ok JEONG  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A    No.6    pp.1416-1424
Publication Date: 2005/06/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.6.1416
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004))
Category: 
Keyword: 
flip-flop,  MTCMOS,  multithreshold-voltage CMOS,  

Full Text: PDF>>
Buy this Article



Summary: 
This paper proposes two high-performance multi-threshold-voltage CMOS (MTCMOS) F/Fs that are based on the CMOS hybrid-latch F/F and the CMOS semi-dynamic F/F. The proposed F/Fs utilize a clock-gating technique or a data recovery circuit in order to preserve their logic states in the power-down mode. They can change operation modes whether the clock level is high or low, and they provide outputs to fanouts in the power-down mode. When compared with existing clock-free MTCMOS F/Fs, the proposed MTCMOS hybrid-latch F/F shows maximum reduction of average delay, average power, and average power-delay product by 33%, 46%, and 63% for the supply voltage ranging from 0.8 V to 1.2 V. Although outperformed by the MTCMOS hybrid-latch F/F, the proposed MTCMOS semi-dynamic F/F inherits the benefit of the embedded logic from the CMOS SD F/F. Experimental results indicate that the MTCMOS semi-dynamic F/F can be used to implement a logic circuit that is superior to the one designed using the MTCMOS hybrid-latch F/F in speed, power, and area.