A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

Mehdi BANIHASHEMI  Khayrollah HADIDI  Abdollah KHOEI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.4   pp.996-1006
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.4.996
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
successive-approximation ADC,  low power,  

Full Text: PDF>>
Buy this Article

A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.