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Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators
Jaesang LIM Jaejoon KIM Beomsup KIM
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E88-A
No.4
pp.1084-1089 Publication Date: 2005/04/01 Online ISSN:
DOI: 10.1093/ietfec/e88-a.4.1084 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: General Fundamentals and Boundaries Keyword: CMOS RF integrated circuits, LC oscillator, phase noise, ring oscillator, noise analysis,
Full Text: PDF>>
Summary:
A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.
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