CMOS Zero-Temperature-Coefficient Point Voltage Reference with Variable-Output-Voltage Level

Hidetoshi IKEDA  Kawori TAKAKUBO  Hajime TAKAKUBO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.2   pp.476-482
Publication Date: 2005/02/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.2.476
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
voltage reference,  zero-temperature-coefficient point,  variable-reference-voltage level,  substrate bias,  CMOS,  

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A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-µm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/ over the temperature range from -100 to 150 at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.