A 0.9 V 1.5 mW Continuous-Time ΔΣ Modulator for W-CDMA

Takeshi UENO  Tetsuro ITAKURA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.2   pp.461-468
Publication Date: 2005/02/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.2.461
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
continuous-time ΔΣ,  OTA,  low-voltage,  W-CDMA,  

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This paper describes a second-order continuous-time ΔΣ modulator for a W-CDMA receiver, which operates at a supply voltage of 0.9 V, the lowest so far reported for W-CDMA. Inverter-based balanced OTAs without using differential pair are proposed for a low-voltage operation. Circuit parameters are optimized by system simulations. The modulator was implemented in a 0.13-µm CMOS technology. It consumes only 1.5 mW. The measured SNDR is 50.9 dB over a bandwidth of 1.92 MHz.