A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures

Toshiki KANAMOTO  Tetsuya WATANABE  Mitsutoshi SHIROTA  Masayuki TERAI  Tatsuya KUNIKIYO  Kiyoshi ISHIKAWA  Yoshihide AJIOKA  Yasutaka HORIBA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.12   pp.3463-3470
Publication Date: 2005/12/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.12.3463
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
SoC,  interconnect,  physical parameter,  low-k,  capacitance,  resistance,  layout parasitic extraction,  

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This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.