
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

SecondOrder Polynomial Expressions for OnChip Interconnect Capacitance
Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E88A
No.12
pp.34533462 Publication Date: 2005/12/01 Online ISSN:
DOI: 10.1093/ietfec/e88a.12.3453 Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance,
Full Text: PDF>>
Summary:
Simple closedform expressions for efficiently calculating onchip interconnect capacitances are presented. The formulas are expressed with secondorder polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 210 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

