Power-Supply Noise Reduction with Design for Manufacturability

Hiroyuki TSUJIKAWA  Kenji SHIMAZAKI  Shozo HIRANO  Kazuhiro SATO  Masanori HIROFUJI  Junichi SHIMADA  Mitsumi ITO  Kiyohito MUKAI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.12   pp.3421-3428
Publication Date: 2005/12/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.12.3421
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power/Ground Network
power integrity,  decoupling capacitor,  power-supply noise,  design for manufacturability (DFM),  chemical mechanical polishing (CMP),  

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In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).