Power-Aware Scalable Pipelined Booth Multiplier

Hanho LEE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.11   pp.3230-3234
Publication Date: 2005/11/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.11.3230
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
power-aware,  pipelined,  Booth multiplier,  low-power,  design,  

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An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications.