A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills

Atsushi KUROKAWA  Toshiki KANAMOTO  Akira KASEBE  Yasuaki INOUE  Hiroo MASUDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.11   pp.3180-3187
Publication Date: 2005/11/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.11.3180
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dummy fill,  dummy metal,  capacitance extraction,  interconnect capacitance,  

Full Text: PDF(489.6KB)>>
Buy this Article




Summary: 
We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.