Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2m)

Chiou-Yng LEE  Che-Wun CHIOU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.11   pp.3169-3179
Publication Date: 2005/11/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.11.3169
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Circuit Theory
finite fields,  bit-parallel systolic multiplier,  Hankel matrix,  dual basis,  normal basis,  

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Normal and dual bases are two popular representation bases for elements in GF(2m). In general, each distinct representation basis has its associated different hardware architecture. In this paper, we will present a unified systolic array multiplication architecture for both normal and dual bases, such a unified multiplication architecture is termed a Hankel multiplier. The Hankel multiplier has lower space complexity while compared with other existing normal basis multipliers and dual basis multipliers.