Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit

Koichi TANNO  Kiminobu SATO  Hisashi TANAKA  Okihiko ISHIZUKA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E88-A   No.10   pp.2696-2698
Publication Date: 2005/10/01
Online ISSN: 
DOI: 10.1093/ietfec/e88-a.10.2696
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
sample hold circuit,  low-voltage circuits,  boost circuits,  MOS analog integrated circuits,  analog circuits,  

Full Text: PDF(257.1KB)>>
Buy this Article




Summary: 
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.