A Comprehensive Simulation and Test Environment for Prototype VLSI Verification

Hidetoshi ONODERA

IEICE TRANSACTIONS on Information and Systems   Vol.E87-D    No.3    pp.630-636
Publication Date: 2004/03/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
simulation,  test,  VLSI,  tester,  verification,  

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This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.