Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits

Kenichi ICHINO  Ko-ichi WATANABE  Masayuki ARAI  Satoshi FUKUMOTO  Kazuhiko IWASAKI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E87-D   No.3   pp.586-591
Publication Date: 2004/03/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Scan Testing
Keyword: 
hybrid BIST,  n-detection test,  partially rotational scan,  low-speed tester,  

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Summary: 
The partially rotational scan (PRS) technique greatly reduces the amount of data needed for n-detection testing. It also enables at-speed testing using low-speed testers. We designed tester intellectual properties (tester IP) with PRS for Viper and COMET II processors. When PRS was applied to a Viper processor, we obtained test data that provided the same fault coverage as with a set of automatic test pattern generation (ATPG) test vectors, although the amount of test data was 16% that of the ATPG. When the PRS technique was applied to a COMET II processor with full-scan design, we obtained test data that provided the same fault coverage as with a set of ATPG test vectors, although the amount of test data was 10% that of the ATPG. We also estimated hardware overhead and test time.