An Analysis of Program and Erase Mechanisms for Floating Channel Type Surrounding Gate Transistor Flash Memory Cells

Masakazu HIOKI  Hiroshi SAKURABA  Tetsuo ENDOH  Fujio MASUOKA  

IEICE TRANSACTIONS on Electronics   Vol.E87-C    No.9    pp.1628-1635
Publication Date: 2004/09/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Flash memory,  Surrounding Gate Transistor (SGT),  floating body,  program and erase operation,  

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This paper analyzes program and erase mechanisms for Floating Channel type Surrounding Gate Transistor (FC-SGT) Flash memory cells for the first time. In FC-SGT Flash memory cell, control gate, floating gate, drain and source is arranged vertically on the substrate. The body region is isolated from the substrate by the bottom source region. The cell is programmed by applying a high positive voltage to the control gate electrode with drain and source electrodes grounded. Erasing is performed by applying a high positive voltage to the drain and source electrodes with the control gate electrode grounded. The physical models for program and erase operations in FC-SGT Flash memory cell are developed. Program and erase operations based on the developed physical models are simulated by utilizing a device simulator. Program and erase characteristics obtained from the device simulation agree well with the results of analytical models. The FC-SGT Flash memory cell can realize program and erase operation with a floating body structure.