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A Design of Compact PLL with Adaptive Active Loop Filter Circuit
Shiro DOSHO Naoshi YANAGISAWA Masaomi TOYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
PLL, adaptive biasing, LPF, compact, 0.15 µm-CMOS,
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This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 µm-CMOS process. The total chip area of the PLL is reduced to 1/2 of the previous one. The jitter performance is almost equal to conventionally biased PLL.