A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits

Hiroaki YAMAOKA  Makoto IKEDA  Kunihiro ASADA  

IEICE TRANSACTIONS on Electronics   Vol.E87-C   No.6   pp.1069-1077
Publication Date: 2004/06/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
PLA,  high-speed,  area-efficient,  dual-rail,  

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This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). In the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-µm CMOS technology with a supply voltage of 1.2 V.